Although in principle applicable to arbitrary integrated circuits, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.
U.S. Patent Publication 2005/0042833 A1, discloses a method of manufacturing an integrated circuit device including a recessed channel transistor. The method includes the steps of defining an active region by forming a trench device isolation region on an integrated circuit substrate, forming a mask pattern on the integrated substrate that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region which is exposed by the mask pattern to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recessed gate that fills the gate trench.
FIG. 15 shows schematic planar view of the geometric arrangement of a recessed channel array transistor as an example of the problems underlying the present invention.
In FIG. 15 a schematic planar view of the active region RT and the isolation region of a recessed channel array transistor is shown. Two cross-sections of the planar view of FIG. 15 are denoted A–A′ and B–B′, respectively.
FIGS. 15A, 7B show two different schematic cross-sections along lines A–A′ and B–B′ of FIG. 15, respectively, of a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor as an example of the problems underlying the present invention.
FIG. 15A shows a cross-section in parallel to the current flow direction, whereas FIG. 15B shows a cross-section perpendicular to the current flow direction.
In FIG. 15A, reference sign 1 denotes the silicon semiconductor substrate. Provided in the silicon semiconductor substrate 1 are isolation trenches IT filled with silicon oxide. In the middle of the transistor cell there is a trench 5 in the flow direction filled with a gate electrode 30 made of polysilicon. Not shown on the trench wall is a gate dielectric 20 made of silicon dioxide. Source and drain regions 40, 50 are provided in the surface area on both sides of the trench 5. Moreover, reference sign 60 denotes a gate electrode contact made of tungsten, and 70 denotes a nitride spacer on both sides of the gate electrode 30 and the gate electrode contact 60.
Problems in such recessed channel array transistors are caused by the overlap of the vertical gate 30 with the highly doped source/drain regions 40, 50. This overlap causes high electrical fields that generate leakage currents in the turned-off state of the transistor. Provided that the planar gate and thus the spacer 70 can be aligned sufficient above the recessed channel device, it can prevent high doping concentrations directly at the gate edge when used as source/drain implant mask. The scalability of the recessed channel array transistor is therefore limited by the alignment of the planar gate.